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256MB - 32Mx64 SDRAM, UNBUFFERED
FEATURES
Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply 144 Pin SO-DIMM * D1: 27.94mm (1.10")
NOTE: Consult factory for availability of: * Lead-Free Products * Vendor source control options * Industrial temperature option
W3DG6433V-D1
DESCRIPTION
The W3DG6433V is a 32Mx64 synchronous DRAM module which consists of four 32Mx16 SDRAM components in TSOP II package, and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
* This product is subject to change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 PIN 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 FRONT DQ13 DQ14 DQ15 VSS NC NC CLK0 VCC RAS# WE# CS0# NC DNU VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 PIN 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 BACK DQ45 DQ46 DQ47 VSS NC NC CKE0 VCC CAS# NC A12 NC NC VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 PIN 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 BACK DQ22 DQ23 VCC A6 A8 VSS A9 A10/AP VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA** VCC PIN 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 BACK DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL** VCC
PIN NAMES
A0 - A12 BA0-1 DQ0-63 CLK0 CKE0 CS0# RAS# CAS# WE# DQMB0-7 VCC VSS SDA SCL DNU NC Address Input (Multiplexed) Select Bank Data Input/Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial Data I/O Serial Clock Do Not Use No Connect
** These pins should be NC in the system which does not support SPD.
March 2005 Rev. 3
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FUNCTIONAL BLOCK DIAGRAM
CS0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQM CS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM CS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
W3DG6433V-D1
LDQM CS# DQ0 DQ1 DQ2 U2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQM CS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
A0 ~ A12, BA0 & 1 RAS# CAS# WE# CKE0 VCC
SDRAM SDRAM SDRAM SDRAM SDRAM CLK0 To all SDRAMs
10 10 SCL 47K
Serial PD
WP SA0 SA1 SA2
SDA
SDRAM SDRAM SDRAM SDRAM
Vss
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 4 50
W3DG6433V-D1
Units V V C W mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, TA = 0C to +70C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= -2mA 3 Note
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data Input/Output Capacitance (DQ0-DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 21 21 21 16 21 11 21 9 Unit pF pF pF pF pF pF pF pF
March 2005 Rev. 3
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OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, 0C TA +70C
W3DG6433V-D1
Version Parameter Operating Current (One bank active) Precharge Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode Symbol ICC1 Conditions Burst Length = 1 tRC tRC(min) IOL = 0mA CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tcc = 10ns Input signals are changed one time during 20ns Io = mA Page burst 4 Banks activated tCCD = 2CK tRC tRC(min) CKE 0.2V 133 440 100 440 Units mA mA mA Note 1
ICC2P ICC3N
14 180
Operating Current (Burst mode)
ICC4
520
520
mA
1
Refresh Current Self Refresh Current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms.
ICC5 ICC6
980 24
980
mA mA
2
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AC OPERATING TEST CONDITIONS
VCC = 3.3V 0.3V, 0 TA 70C Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Value 2.4/0.4 1.4 tR/tF = 1/1 1.4
W3DG6433V-D1
Unit V V ns V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS# to CAS# delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol 7.5, 10 tRRD (min) tRCD (min) tRP (min) tRAS (min) tRAS (max) tRC (min) tRDL (min) tDAL (min) tCDL (min) tBDL (min) tCCD (min) CAS latency=3 CAS latency=2 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 ns ns ns ns us ns CLK -- CLK CLK CLK ea 2 2 3 4 1 2 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
March 2005 Rev. 3
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PACKAGE DIMENSIONS FOR D1
Ordering Information W3DG6433V10D1 W3DG6433V75D1 Speed 100MHz 133MHz CAS Latency CL=2 CL=3
W3DG6433V-D1
Height* 27.94 (1.10") 27.94 (1.10")
NOTES: * Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. Please add "-M" for Micron or "-S" for Samsung to the back of the part number for the specific component vendor preferred. * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D1
67.72 (2.661 Max) 2.01 (0.079 Min) 2.54 (0.10) MAX.
251
WEDC
3.99 (0.157)
19.99 (0.787)
27.94 (1.10) Max
23.14 (0.913) 28.2 (1.112)
32.79 (1.291) 4.60 (0.181) 1.50 (0.059)
9.91 (0.039) ( 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
March 2005 Rev. 3
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
256MB - 32Mx64 SDRAM UNBUFFERED
W3DG6433V-D1
Revision History Rev #
Rev 0 Rev 1
History
Created 1.1 Removed "ED" from part number 1.2 Updated CAP and IDD specs
Release Date
11-01 6-04
Status
Advanced Preliminary
Rev 2
2.1 Updated block diagram 2.2 Updated package dimensions 2.3 Added lead-free and RoHS notes 2.4 Added source control options 2.5 Added industrial temperature option 2.6 Added AC Specs
1-05
Preliminary
Rev 3
3.1 Updated ICC Specs 3.2 Move from Preliminary to Final
3-05
Final
March 2005 Rev. 3
7
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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